Synchronous buck converters are used for voltage regulation. A typical synchronous buck converter can use a controller IC (integrated circuit), a high-side power MOSFET and a low-side power MOSFET.
FIG. 1 shows a simplified circuit diagram of a typical synchronous buck converter. Synchronous buck converter (SBC) 10 includes a high-side metal oxide semiconductor field effect transistor (MOSFET) 12 and a low-side MOSFET 14. The drain D of the low-side MOSFET 14 is electrically connected to the source S of the high-side MOSFET 12, through a node S. A PWM (pulse width modulator) controller can control the gates G of the high and low-side MOSFETs 12, 14.
The node connection between the source S and the drain D of the high and low-side MOSFETs 12 and 14, respectively, in SBC 10, desirably has very low inductance in order for the SBC 10 to be used at moderate to high operating/switching frequencies. Where MOSFETs 12 and 14 are configured as discrete devices, the design of the circuit layout of SBC 10 is desirably optimized to reduce parasitic inductances. Alternatively, SBC 10 can be configured as a fully-integrated synchronous buck converter in a single converter in a single package, which is designed and laid out to reduce parasitic inductances in the connection between the source S and the drain D of the high and low-side MOSFETs 12 and 14, respectively. Such fully integrated devices, however, tend to be fairly application and/or design specific devices that are often not compatible with other applications and/or designs. Further, the printed circuit board traces/conductors that connect the MOSFETs are typically not well-suited to carrying moderate to high levels of current.
In a synchronous buck converter using conventional packages, the high side MOSFET source is connected to a low side MOSFET drain with bond wires. This creates high parasitic inductance. In addition, in conventional packages, the connection of the driver IC to the high side and low side MOSFET gate, source and drain is also performed using bond wires and individual die paddles that support the MOSFETs. Using individual paddles requires the use of longer bond wires. Such factors reduce the high-frequency power efficiency and thermal performance of conventional packages. In general, multi-die paddle packages have a lower package reliability level than embodiments of the invention. Moreover, in general, multi die paddle devices are laterally arranged as a result of which the physical size of the package is larger leading to lower package reliability (e.g. sensitivity to moisture during reflow/soldering/mounting processes). In addition, the conventional package does not dissipate heat well, and it would be desirable to improve the heat dissipation properties of packages of this type.
Accordingly, it would be desirable to provide for improved semiconductor die packages, methods for making semiconductor die packages, and electrical assemblies using such semiconductor die packages.